1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a dynamic random access memory (DRAM) with a vertical pass transistor.
2. Description of Related Art
A memory device with higher cell density naturally has a higher memory capacity, and accordingly has a lower fabrication cost. In order to increase the memory capacity in a DRAM device, a strategy to increase a memory cell density is generally taken. A higher device density is usually achieved by reducing structures dimension of an integrated circuit (IC), such as line width, line pitch distance, transistor gate, or coupled capacitor.
A DRAM cell typically includes a field-effect transistor (FET) and a capacitor coupled to the FET. A DRAM device usually includes a large number of DRAM cells arranged in an array structure. Each DRAM cell can store one binary data through a capacitor charge status. A charged capacitor stores a binary data of "1", and a discharged capacitor stores a binary data of "0". The action of charging or discharging is done by its coupled FET through a voltage status applied on its drain region. A desired FET can also be selected by a bit line and a word line. The world line is typically coupled to each gate of the FETs in the DRAM array, and the bit line is typically coupled to each drain of the FETs of the DRAM array. The bit line provides the voltage status to the FET. The world line is used to turn on/off the FET. Through a selected pair of the bit line and the world line, a desired FET is selected and is written-in a binary data to the coupled capacitor. The stored binary data can also be read out by selecting the FET and switching the bit line to a comparator circuit to obtain the charge status of the coupled capacitor. The stored binary data in the selected DRAM cell is therefore obtained.
The capacitor stores charges on its lower and upper electrode surfaces, which are separated by a dielectric layer. The lower electrode is coupled to the source of the FET. The amount of stored charges in one capacitor depends on its capacitance. The capacitance is proportional to its electrode surface, such as the lower electrode surface, inversely proportional to the distance between the upper electrode and the lower electrode, and proportional to the dielectric constant.
In order to reduce the device dimension, the surface of the lower electrode is usually also reduced. In this manner, its capacitance is reduced. If the capacitance of the capacitor is reduced, a lot of issues may be induced. For example, a decay mechanism and a charge leakage may cause an error content of the stored binary data due to small quantity of stored charges, which therefore has small tolerance of charge variance. Generally, in order to prevent the error content of the stored binary data, the capacitor is necessarily refreshed in a certain period of time, which is also called a refreshing cycle time. If the capacitance is smaller, the refreshing cycle time is shorter, and the refreshing process is necessarily more often performed. During each time of the refreshing process, the DRAM can not fulfills its function. This is called a dead time. A smaller capacitance has more dead time, and the efficiency of the DRAM performance is reduced. Moreover, a smaller capacitance needs a more sensitive amplifier, which cause a more complicated circuit and a more fabrication cost.
In order to maintain sufficient capacitance in the DRAM cell as the device dimension is reduced, several similar conventional capacitor structures have been proposed. A typical one is shown in FIGS. 1A-1C, which are cross-sectional views of a portion of a substrate, schematically illustrating a conventional fabrication process for forming a capacitor on a FET. In FIG. 1A, a gate 106, a gate oxide layer 104, and an interchangeable source/drain region 108 serving together as a metal-oxide semiconductor (MOS) transistor are formed on a semiconductor substrate 100. A shallow trench isolation (STI) structure 102 is also formed in the substrate 100 to isolate the MOS transistor. A dielectric layer 110 is formed over the substrate 100. A contact plug 112 is formed in the dielectric layer 110 to have an electrical coupling to the interchangeable source/drain region.
In FIG. 1B, a conductive layer 114 is formed over the substrate 100 so as to be electrically coupled to the interchangeable source/drain region 108 through the contact pug 112.
In FIG. 1B and FIG. 1C, the conductive layer 114 is patterned to remove a side portion of the conductive layer 114 so that a remaining portion of the conductive layer 114 becomes a conductive layer 114a, which covers the contact plug 112 and its surrounding region. The conductive layer 114a and the contact plug 112 serve as a lower electrode of a capacitor, which is electrically coupled to the interchangeable source/drain. A conformal hemispherical silicon grain (HSG) layer 115 is formed on the conductive layer 114a. Since the HSG layer 115 includes several hemispherical structures, the total surface area is increased, and the capacitance is consequently increased without consuming much of the available area of the substrate 100. A dielectric thin film 116 is formed on the HSG layer 115. An upper electrode 118 is formed on the dielectric thin film 116 so as to accomplish a fabrication of the capacitor coupled the to a MOS transistor. This MOS transistor with a capacitor serve as a cell in a DRAM device.
In the conventional method for fabricating a DRAM cell as described above, the formation is limited by a spatial resolution resulting from a light source used in photolithography, and an alignment precision in each process. All substructures, such as The gate width, line width, aperture of contact opening, a distance between the gate and the contact opening, and so on have their dimension limitation. Moreover, in the conventional DRAM cell structure, the bit line, the gate structure, and the capacitor are horizontally distributed. The available area of substrate for one DRAM cell is necessarily shared by the MOS transistor and the capacitor. This causes the DRAM cell dimension not to be largely reduced.
Furthermore, since the capacitor is directly coupled to the junction region, which is the interchangeable source/drain region, a junction leakage may further induce the charge leakage of the capacitor. This causes a shorter refreshing cycle time. The refreshing process is performed more frequently. The accumulated dead time of the DRAM device is increased. So, the DRAM performance is very inefficient.